This invention relates to detector circuits and in particular, to dynamic sense-refresh detector amplifiers useful in dynamic random access memory (RAM) systems.
U.S. Pat. No. 4,028,557, in which there is a common assignee with the present patent application, teaches a dynamic sense-refresh amplifier which is characterized by relatively low power dissipation, relatively high operating noise margin, and the capability to refresh logic information to full "1" and "0" levels. One potential problem with this sense-refresh amplifier is that during the refresh operation some of the signal used to aid in refresh is lost and it is possible under some conditions for a full "1" level not to be obtained. In addition, it is possible that the capacitive charging and discharging of the load-sense circuits will not always return these circuits to the initial potential levels. This can somewhat reduce operating noise margins.